Welcome To b2b168.com, Join Free | Sign In
中文(简体) |
中文(繁體) |
Francés |Deutsch |Pусский |
| No.12967552
- Product Categories
- Friendly Links
Information Name: | 6ES5-243-1AA13 |
Published: | 2014-03-26 |
Validity: | 3000 |
Specifications: | 6ES5-243-1AA13 |
Quantity: | 1.00 |
Price Description: | |
Detailed Product Description: | Traditional conventional computer systems located inside its memory controller chipset Northbridge, CPU and memory to exchange data, you need to go through "CPU - Northbridge - Memory - Northbridge - CPU" 5 steps, in this mode data transmission via multi-level data delayed apparently relatively large and thus affecting the overall performance of computer systems; integrated integrated memory controller is on the CPU board incorporates a memory controller, memory controller did not let us talk about how the system works . 26 Data A ~ Z, to be sent to the CPU, this time to give instructions to the CPU North Bridge (because the memory controller is integrated in the Northbridge, say so to go through the North Bridge), the memory through the memory controller receives a command, this command is transferring data from memory A ~ Z b units to the CPU, memory began to take data at this time, which is usually referred to addressing. When the memory to find this data, which is 26 data for each data 500MB, the sum of all the data on approximately 12GB, assuming memory is dual channel R2 800, the data transfer rate is multiplied to 800MHZ divided by 8 bits per byte 128BIT = 12GB per second, through analysis, that just one second can be sent to the CPU, the data at this time in the second time only sent to the Northbridge memory controller in Northbridge, Northbridge how data is sent to the CPU it, This would be through the FSB FSB, the assumption that the FSB frequency 800MHZ, then the data transfer rate is to multiply 64BIT 800MHZ divided by 8 bits per second = 6.4GB per second, from Northbridge to the CPU to 2 seconds, so the data is transferred to The total CPU time is 3 seconds, then look at how CPU integrated memory controller when the system is working; transfer data from memory to the controller, the same as one second, the difference is that this time, no longer by slow swallow swallow the FSB, CPU reads the data from the memory controller directly on the line, because the memory controller in the CPU door Luo, an analogy, a thing in your door, you can directly took that This principle, forget about, CPU integrated memory controller reads 12GB of data is only used one second of time, so significant savings in computation time, but also give full play to the performance of the CPU. To sum up: When the CPU is not the memory controller: transmit data to the memory controller --- Northbridge ---- CPU's memory controller when: ------ CPU memory controller data to the transmission, one step. [1] 2 advantages editor works inside the CPU integrated memory controller that can effectively control the memory controller with the CPU core to work on the same frequency, but also due to the exchange of data between memory and the CPU without going through the North Bridge, can effectively reduce transmission delay. Analogy, it is like moving the goods warehouse directly next to the processing plant, greatly reducing raw material and finished goods in the warehouse and processing plant between the time needed to transport back and forth, greatly improved production efficiency. Thus the overall performance of the system has also been improved. [2] Like the memory frequency and CPU, memory, also has its own operating frequency, the frequency in MHz memory clock speed higher to some extent represents the memory can be achieved faster. The frequency determines the maximum memory can work memory of what frequency. Most mainstream memory frequency of DDR2-800 and DDR3-1333, as a replacement for DDR2, DDR3 memory frequency has been marching to 3000MHz. Memory capacity of memory is not only influencing factors memory prices, but also the factors affecting the performance of the whole system. Past the Windows XP platform, 512M memory is still the mainstream, 1GB is already a large capacity; 64 system began to spread, Windows Vista, Windows 7 and more people to use, so there is no memory 2GB not necessarily guarantee fluency operation. Single main memory capacity of 1GB, 2GB, 4GB, has reached the highest single 8GB. The normal operating voltage of the memory voltage needed for the work, the different types of memory voltage is different, but each has its own specifications, beyond its specifications, likely to cause memory corruption. DDR2 memory operating voltage is generally about 1.8V, and DDR3 memory at around 1.6V. Some high-frequency memory needs to work under a voltage higher than the standard value, specific to each brand and each model of memory, will depend on the manufacturers. Just within the allowed range of floating, slightly increased memory voltage is conducive to memory overclocking, but at the same time greatly increase the heat, so there is risk of damage to the hardware. Timing Parameters tCL: CAS Latency Control (tCL) generally when we access memory timing parameters, such as "8-8-8-24" This kind of number sequence, a sequence of numbers corresponding to the above parameters is "CL-tRCD- tRP-tRAS ". The first "8" is the first one parameter, namely CL parameters. CAS Latency Control (also described as tCL, CL, CAS Latency Time, CAS Timing Delay), CAS latency is "read and write memory address controller latency forefront." CAS receives a command from the control time to execute instructions. Because the CAS main control hexadecimal address, or a memory matrix column address, it is the most important parameter in the stability of the design should be as low. Memory is based on the row and column addressing, when the request triggers, originally tRAS (Activeto Precharge Delay), after pre-charging, memory really starts to initialize RAS. Once tRAS activation, RAS (Row Address Strobe) to begin addressing the need of the data. First row address, then initialize tRCD, the end of the cycle, and then access the precise data required hexadecimal address by CAS. CAS period from the beginning to the end is the CAS CAS latency. So CAS is the final step to find the data, but also the memory of the most important parameters. This parameter controls the data memory receives a read command after how many clock cycles to wait before actually executing the command. Meanwhile, the parameter also determines the number of clock cycles to complete the first part of the transmission in a memory burst transfer process needs. This parameter is smaller, faster memory. Care must be taken not to run in the lower part of the memory latency, data may be lost. And improve memory latency can run at higher frequencies, so the need for memory overclocking, you should try to improve the CAS latency. The impact of the parameters on the maximum memory performance, the premise of guaranteeing the stability of the system, the lower the CAS value, will result in faster memory read and write operations. tRCD: RAS to CAS Delay This value is the "8-8-8-24" memory timing parameters in the first two parameters, namely, the first two "8." RAS to CAS Delay (also described as: tRCD, RAS to CAS Delay, Active to CMD), said, "OK addressed to the column address delay time", the smaller the value, the better the performance. Memory read, write or refresh operation, you need to be inserted between the two pulse signal delay clock cycles. In the JEDEC specification, which is ranked second parameter to reduce this delay, you can improve system performance. If your memory overclocking performance is poor, you can set this value to the default value of memory or try to improve tRCD value. tRP: Row Precharge Timing (tRP) This value is the "8-8-8-24" memory timing parameters in the first three parameters, namely the first three "8." Row Precharge Timing (also described as: tRP, RAS Precharge, Precharge to active), that "the controller memory row address precharge time", the smaller pre-charging parameters faster memory access. tRP before another row is set to be activated, RAS required charging time. tRAS: Min RAS Active Timing value is the value that is "8-8-8-24" memory timing parameters in the last parameter, namely "24." Min RAS Active Time (also described as: tRAS, Active to Precharge Delay, Row Active Time, Precharge Wait State, Row Active Delay, Row Precharge Delay, RAS Active Time), said "the memory line is valid to precharge the shortest period." adjusting this parameter requires a combination of specific circumstances, generally located between our best 24 to 30. This parameter according to the actual situation, not to say that the larger or the smaller the better. If the tRAS period is too long, the system will wait because of unnecessary and degrade performance. Lower tRAS period will cause the row has been activated earlier addresses into a non-active state. If the tRAS period is too short, it may due to lack of sufficient time and burst data transfer can not be completed, this will lead to loss of data or damage to data. This value is generally set to CAS latency + tRCD + 2 clock cycles. For most people, this small hardware selected memory capacity and frequency, and then plug in the motherboard to spend on the line, it's a lot of small parameter completely do not care. So, industry vendors will provide a more fool-parameter information read memory SPD chip automatically set the small parameter, easy to use; more simple overclocking settings - XMP technology that allows ordinary users can easily enjoy Overclocking added fun. Of course, the real players in the OC in order to achieve the best results, still prefer to manually set the small parameter. I hope through this article for the parameters that we can have a deeper understanding of memory, and will certainly help in the use. [3] |
Admin>>>
You are the 3600 visitor
Copyright © GuangDong ICP No. 10089450, Rui Hai-Kun Automation Equipment Co., Ltd. All rights reserved.
Technical support: ShenZhen AllWays Technology Development Co., Ltd.
AllSources Network's Disclaimer: The legitimacy of the enterprise information does not undertake any guarantee responsibility
You are the 3600 visitor
Copyright © GuangDong ICP No. 10089450, Rui Hai-Kun Automation Equipment Co., Ltd. All rights reserved.
Technical support: ShenZhen AllWays Technology Development Co., Ltd.
AllSources Network's Disclaimer: The legitimacy of the enterprise information does not undertake any guarantee responsibility